1. Field of the Invention
The invention relates generally to testing electrical circuits and, more particularly, to testing a phase-locked loop (PLL).
2. Description of the Related Art
Full characterization of a phase-locked loop (PLL) can involve both a large number of tests and lengthy time for each test due to the large time constants within the PLL circuit and the variability that process, temperature, and supply voltage have on PLL performance. Lock range and capture range tests are standard tests implemented at a manufacturing level, but these tests must be limited in number to keep test time reasonable and inexpensive, preventing full PLL characterization.
Therefore, a need exists for a system and method for fully characterizing a PLL with reduced number of tests.